 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14490 Hex Contact Bounce Eliminator The MC14490 is constructed with complementary MOS enhancement mode devices, and is used for the elimination of extraneous level changes that result when interfacing with mechanical contacts. The digital contact bounce eliminator circuit takes an input signal from a bouncing contact and generates a clean digital signal four clock periods after the input has stabilized. The bounce eliminator circuit will remove bounce on both the "make" and the "break" of a contact closure. The clock for operation of the MC14490 is derived from an internal R-C oscillator which requires only an external capacitor to adjust for the desired operating frequency (bounce delay). The clock may also be driven from an external clock source or the oscillator of another MC14490 (see Figure 5). NOTE: Immediately after power-up, the outputs of the MC14490 are in indeterminate states. * * * * * * * * * * * * Diode Protection on All Inputs Six Debouncers Per Package Internal Pullups on All Data Inputs Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line Internal Oscillator (R-C), or External Clock Source TTL Compatible Data Inputs/Outputs Single Line Input, Debounces Both "Make" and "Break" Contacts Does Not Require "Form C" (Single Pole Double Throw) Input Signal Cascadable for Longer Time Delays Schmitt Trigger on Clock Input (Pin 7) Supply Voltage Range = 3.0 V to 18 V Chip Complexity: 546 FETs or 136.5 Equivalent Gates BLOCK DIAGRAM +VDD DATA 4-BIT STATIC SHIFT REGISTER SHIFT OSCin 7 OSCout 9 Bin 14 Cin 3 Din 12 Ein 5 Fin 10 OSCILLATOR AND TWO-PHASE CLOCK GENERATOR 1 2 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 1 IDENTICAL TO ABOVE STAGE 2 6 Fout 2 11 Eout 2 4 Dout 2 13 Cout LOAD 1 2 1 2 2 Bout 1 2 VDD = PIN 16 VSS = PIN 8 1/2-BIT DELAY 15 Aout L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION MC14490P MC14490L MC14490DW Plastic Ceramic SOIC TA = - 55 to 125C for all packages. Ain 1 REV 3 1/94 (c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14490 297 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I IIIIIIIIII III IIII I III IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIII IIIIII IIII I I I II II II III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I IIIIIII I I I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 MW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C to 125_C ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) MAXIMUM RATINGS* (Voltages Referenced to VSS) Quiescent Current (Vin = VSS or VDD, Iout = 0 A) Input Capacitance Pullup Resistor Source Current Debounce Inputs (Vin = VSS) Input Current Oscillator -- Pin 7 (Vin = VSS or VDD) Input Current Debounce Inputs (Vin = VDD) Output Drive Current Oscillator Output (VOH = 2.5 V) (VOH = 4.6 V) (VOH = 9.5 V) (VOH = 13.5 V) Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) Output Voltage Vin = VDD or 0 Vin, Vout MC14490 298 Symbol VDD Tstg PD (VO = 0.5 or 4.5 Vdc) "1 Level" (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Vin = 0 or VDD Iin Debounce Outputs (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V) Oscillator Output (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V) Debounce Outputs (VOH = 2.5 V) (VOH = 4.6 V) (VOH = 9.5 V) (VOH = 13.5 V) Characteristic Storage Temperature Power Dissipation, per Package Input Current (DC or Transient), per Pin Input or Output Voltage (DC or Transient) DC Supply Voltage "1" Level "0" Level Parameter Source Sink Symbol VOH VOL IOH VIH ISS IOL Cin VIL IIH IIL Iin VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 -- - 0.5 to VDD + 0.5 - 0.9 - 0.19 - 0.6 1.8 - 0.6 - 0.12 - 0.23 - 1.4 4.95 9.95 14.95 - 0.5 to + 18.0 0.36 0.9 4.2 - 65 to + 150 Min 175 340 505 2.6 4.0 12 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- - 55_C Value 10 500 620 375 740 1100 0.05 0.05 0.05 Max 150 280 840 2.0 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 0.75 - 0.16 - 0.5 - 1.5 Unit mW 4.95 9.95 14.95 mA - 0.5 - 0.1 - 0.2 - 1.2 _C 0.3 0.75 3.5 Min 140 280 415 V V 2.2 3.3 10 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- - 2.2 - 0.46 - 1.2 - 4.5 Typ # 255 25_C - 1.5 - 0.3 - 0.8 - 3.0 2.75 5.50 8.25 2.25 4.50 6.75 40 90 225 190 380 570 5.0 0.2 4.0 9.0 35 0.9 2.3 10 5.0 10 15 0 0 0 MOTOROLA CMOS LOGIC DATA 400 OSCin 0.05 0.05 0.05 Max 100 225 650 255 500 750 7.5 2.0 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Dout Bout VSS Fout Cin Ain Ein PIN ASSIGNMENT 8 7 6 5 4 3 2 1 - 0.6 - 0.12 - 0.4 - 1.2 - 0.4 - 0.08 - 0.16 - 1.0 4.95 9.95 14.95 0.24 0.6 2.8 Min 70 145 215 1.8 2.7 8.1 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- 125_C 12 13 14 15 16 10 11 9 250 0.05 0.05 0.05 Max 90 180 550 1.5 3.0 4.0 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 225 440 660 OSCout Fin Eout Din Cout Bin VDD Aout mAdc mAdc Adc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II III I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ # 180 90 65 100 50 40 60 30 20 Max 360 180 130 200 100 80 120 60 40 570 240 190 740 320 240 1.4 3.0 4.5 -- -- -- Unit ns Output Rise Time All Outputs Output Fall Time Oscillator Output ns tTHL tTHL Debounce Outputs Propagation Delay Time Oscillator Input to Debounce Outputs tPHL ns 285 120 95 370 160 120 2.8 6 9 50 40 30 tPLH Clock Frequency (50% Duly Cycle) (External Clock) Setup Time (See Figure 1) fcl MHz tsu 100 80 60 ns Maximum External Clock Input Rise and Fall Time Oscillator Input Oscillator Frequency OSCout Cext 100 pF* tr, tf ns No Limit fosc, typ Note: These equations are intended to be a design guide. Laboratory experimentation may be required. Formulas are typically 15% of actual frequencies. 1.5 Cext (in F) 4.5 Cext (in F) 6.5 Cext (in F) Hz * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. *POWER-DOWN CONSIDERATIONS Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the turn-off time of the power supply must not be faster than t = (VDD - VSS) Cext / (10 mA). For example, If VDD - VSS = 15 V and Cext = 1 F, the power supply must turn off no faster than t = (15 V) (1 F) / 10 mA = 1.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2. OSCin tPLH Aout 50% 50% 90% 10% tr tPHL 90% 10% 50% tf OSCin 50% tsu Ain 50% VDD 0V VDD 0V MC14490 VDD 7 OSCin 9 OSCout VDD 0V D1 Cext D2 VDD Aout Figure 1. Switching Waveforms MOTOROLA CMOS LOGIC DATA Figure 2. Discharge Protection During Power Down MC14490 299 THEORY OF OPERATION The MC14490 Hex Contact Bounce Eliminator is basically a digital integrator. The circuit can integrate both up and down. This enables the circuit to eliminate bounce on both the leading and trailing edges of the signal, shown in the timing diagram of Figure 3. Each of the six Bounce Eliminators is composed of a 4-1/2-bit register (the integrator) and logic to compare the input with the contents of the shift register, as shown in Figure 4. The shift register requires a series of timing pulses in order to shift the input signal into each shift register location. These timing pulses (the clock signal) are represented in the upper waveform of Figure 3. Each of the six Bounce Eliminator circuits has an internal resistor as shown in Figure 4. A pullup resistor was incorporated rather than a pulldown resistor in order to implement switched ground input signals, such as those coming from relay contacts and push buttons. By switching ground, rather than a power supply lead, system faults (such as shorts to ground on the signal input leads) will not cause excessive currents in the wiring and contacts. Signal lead shorts to ground are much more probable than shorts to a power supply lead. When the relay contact is closed, (see Figure 4) the low level is inverted, and the shift register is loaded with a high on each positive edge of the clock signal. To understand the operation, we assume all bits of the shift register are loaded with lows and the output is at a high level. At clock edge 1 (Figure 3) the input has gone low and a high has been loaded into the first bit or storage location of the shift register. Just after the positive edge of clock 1, the input signal has bounced back to a high. This causes the shift register to be reset to lows in all four bits -- thus starting the timing sequence over again. During clock edges 3 to 6 the input signal has stayed low. Thus, a high has been shifted into all four shift register bits and, as shown, the output goes low during the positive edge of clock pulse 6. It should be noted that there is a 3-1/2 to 4-1/2 clock period delay between the clean input signal and output signal. In this example there is a delay of 3.8 clock periods from the beginning of the clean input signal. After some time period of N clock periods, the contact is opened and at N + 1 a low is loaded into the first bit. Just after N + 1, when the input bounces low, all bits are set to a high. At N + 2 nothing happens because the input and output are low and all bits of the shift register are high. At time N + 3 and thereafter the input signal is a high, clean signal. At the positive edge of N + 6 the output goes high as a result of four lows being shifted into the shift register. Assuming the input signal is long enough to be clocked through the Bounce Eliminator, the output signal will be no longer or shorter than the clean input signal plus or minus one clock period. The amount of time distortion between the input and output signals is a function of the difference in bounce characteristics on the edges of the input signal and the clock frequency. Since most relay contacts have more bounce when making as compared to breaking, the overall delay, counting bounce period, will be greater on the leading edge of the input signal than on the trailing edge. Thus, the output signal will be shorter than the input signal -- if the leading edge bounce is included in the overall timing calculation. The only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state. Referring to Figure 3, a false state is seen to occur three times at the beginning of the input signal. The input signal goes low three times before it finally settles down to a valid low state. The first three low pulses are referred to as false states. If the user has an available clock signal of the proper frequency, it may be used by connecting it to the oscillator input (pin 7). However, if an external clock is not available the user can place a small capacitor across the oscillator input and output pins in order to start up an internal clock source (as shown in Figure 4). The clock signal at the oscillator output pin may then be used to clock other MC14490 Bounce Eliminator packages. With the use of the MC14490, a large number of signals can be cleaned up, with the requirement of only one small capacitor external to the Hex Bounce Eliminator packages. 1 OSCin OR OSCout 2 3 4 5 6 N+1 N+3 N+5 N+7 INPUT OUTPUT CONTACT OPEN CONTACT BOUNCING CONTACT CLOSED (VALID TRUE SIGNAL) CONTACT OPEN CONTACT BOUNCING Figure 3. Timing Diagram MC14490 300 MOTOROLA CMOS LOGIC DATA +VDD Ain 1 "FORM A" CONTACT OSCin 7 Cext OSCout 9 PULLUP RESISTOR (INTERNAL) DATA 4-BIT STATIC SHIFT REGISTER SHIFT LOAD 1/2 BIT DELAY 1 2 15 Aout OSCILLATOR AND TWO-PHASE CLOCK GENERATOR 1 2 1 2 Figure 4. Typical "Form A" Contact Debounce Circuit (Only One Debouncer Shown) OPERATING CHARACTERISTICS The single most important characteristic of the MC14490 is that it works with a single signal lead as an input, making it directly compatible with mechanical contacts (Form A and B). The circuit has a built-in pullup resistor on each input. The worst case value of the pullup resistor (determined from the Electrical Characteristics table) is used to calculate the contact wetting current. If more contact current is required, an external resistor may be connected between VDD and the input. Because of the built-in pullup resistors, the inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V. At this voltage, the input should be driven with paralleled standard gates or by the MC14049 or MC14050 buffers. The clock input circuit (pin 7) has Schmitt trigger shaping such that proper clocking will occur even with very slow clock edges, eliminating any need for clock preshaping. In addition, other MC14490 oscillator inputs can be driven from a single oscillator output buffered by an MC14050 (see Figure 5). Up to six MC14490s may be driven by a single buffer. The MC14490 is TTL compatible on both the inputs and the outputs. When VDD is at 4.5 V, the buffered outputs can sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a result of the internal input pullup resistors. OSCin 7 Cext 1/6 MC14050 NO CONNECTION 9 OSCout OSCin 7 9 OSCout FROM CONTACTS MC14490 TO SYSTEM LOGIC FROM CONTACTS MC14490 TO SYSTEM LOGIC OSCin 7 NO CONNECTION 9 OSCout FROM CONTACTS MC14490 TO SYSTEM LOGIC Figure 5. Typical Single Oscillator Debounce System MOTOROLA CMOS LOGIC DATA MC14490 301 TYPICAL APPLICATIONS ASYMMETRICAL TIMING In applications where different leading and trailing edge delays are required (such as a fast attack/slow release timer.) Clocks of different frequencies can be gated into the MC14490 as shown in Figure 6. In order to produce a slow attack/fast release circuit leads A and B should be interchanged. The clock out lead can then be used to feed clock signals to the other MC14490 packages where the asymmetrical input/output timing is required. IN OUT MULTIPLE TIMING SIGNALS As shown in Figure 8, the Bounce Eliminator circuits can be connected in series. In this configuration each output is delayed by four clock periods relative to its respective input. This configuration may be used to generate multiple timing signals such as a delay line, for programming other timing operations. One application of the above is shown in Figure 9, where it is required to have a single pulse output for a single operation (make) of the push button or relay contact. This only requires the series connection of two Bounce Eliminator circuits, one inverter, and one NOR gate in order to generate the signal AB as shown in Figures 9 and 10. The signal AB is four clock periods in length. If the inverter is switched to the A output, the pulse AB will be generated upon release or break of the contact. With the use of a few additional parts many different pulses and waveshapes may be generated. OSCin MC14490 OSCout MC14011B 1 A EXTERNAL CLOCK fC /N B fC/N 14 B.E. 2 B.E. 1 Ain 15 Aout 2 Figure 6. Fast Attack/Slow Release Circuit LATCHED OUTPUT The contents of the Bounce Eliminator can be latched by using several extra gates as shown in Figure 7. If the latch lead is high the clock will be stopped when the output goes low. This will hold the output low even though the input has returned to the high state. Any time the clock is stopped the outputs will be representative of the input signal four clock periods earlier. IN OUT Bin 3 B.E. 3 Cin 12 Din 5 Ein 10 6 11 4 13 Bout Cout B.E. 4 Dout B.E. 5 Eout MC14490 OSCin OSCout MC14011B CLOCK OSCin LATCH = 1 UNLATCH = 0 7 Fin B.E. 6 Fout CLOCK 9 OSCout Figure 8. Multiple Timing Circuit Connections Figure 7. Latched Output Circuit MC14490 302 MOTOROLA CMOS LOGIC DATA IN A IN BE 1 OUT A OUT B AB BE 2 A ACTIVE LOW B ACTIVE LOW B Figure 9. Single Pulse Output Circuit OSCin OR OSCout INPUT A B C D E F AB AB Figure 10. Multiple Output Signal Timing Diagram This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA MC14490 303 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 -B- 1 8 C L -T- SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M MC14490 304 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 -B- 1 8 8X P 0.010 (0.25) M B M 16X D M J TA S 0.010 (0.25) B S F R X 45 _ C -T- 14X DIM A B C D F G J K M P R G K SEATING PLANE M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CMOS LOGIC DATA *MC14490/D* MC14490 MC14490/D 305 |
Price & Availability of MC14490L
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |